Random Access Memory is the computer's primary short-term working memory. Unlike storage (SSDs, HDDs) which retains data indefinitely, RAM is volatile — it requires constant power to maintain its contents. The moment power is removed, all data is instantly lost. This fundamental characteristic drives the persistent memory problem in computer science: every useful piece of data must be loaded from storage into RAM before the CPU can use it. The term "random access" distinguishes RAM from sequential-access storage like magnetic tape — any memory location can be accessed in the same time regardless of its position. This is achieved through an addressing system where each byte has a unique numerical address. The CPU's memory controller selects a row and column in the DRAM array using address lines, then reads or writes data on the data bus. DRAM (Dynamic RAM) stores each bit as a charge on a tiny capacitor, paired with a transistor. The capacitor leaks charge over time — after ~64 milliseconds, the charge dissipates enough that a 1 becomes indistinguishable from a 0. To prevent data loss, the memory controller must continuously "refresh" every row — reading and rewriting the charge. This refresh cycle periodically locks rows and prevents access, contributing to RAM latency. Modern DDR5 RAM reduces this overhead with on-die ECC and partial array self-refresh. The memory hierarchy's purpose is bridging the 500× latency gap between processors and DRAM. An L1 cache miss costs ~5ns. An L2 cache miss costs ~12ns. An L3 cache miss forces a DRAM access at ~70ns (DDR5). Modern CPUs implement sophisticated hardware prefetchers that analyze access patterns and preload data from RAM into cache before it's explicitly requested, hiding much of the DRAM latency from the executing code. Dual-channel (and quad-channel) operation doubles (quadruples) the memory bus width. A single DDR5-6000 stick provides 64-bit wide access at 6,000 MT/s = 48 GB/s peak bandwidth. Two matched sticks in dual-channel widen the bus to 128 bits = 96 GB/s. For CPU-bound workloads where the memory bus is the bottleneck — particularly in integrated GPU systems where the iGPU shares the same RAM — dual-channel can improve performance by 30–50%. DDR5 also introduced per-stick 32-bit sub-channels (each DIMM has two independent 32-bit channels), improving efficiency even in single-DIMM configurations.