The Central Processing Unit is the primary computational engine of every computer. It executes the fundamental instruction cycle — Fetch, Decode, Execute, Write-back — at speeds measured in billions of cycles per second (GHz). Every program, every calculation, every decision made by software ultimately reduces to a sequence of these basic operations. The fetch stage retrieves the next instruction from memory (ideally from the L1 instruction cache, a tiny but extremely fast SRAM buffer a few kilobytes in size). The decode stage parses the machine instruction binary encoding and determines what operation to perform and on which data. The execute stage passes the decoded operation to the appropriate execution unit — an ALU (Arithmetic Logic Unit) for integer math, an FPU (Floating Point Unit) for decimal math, or a SIMD unit for vector operations. The write-back stage stores the result to a register or cache. Modern CPUs dramatically accelerate this cycle through pipelining — breaking the execution cycle into many discrete stages so multiple instructions can be in different stages simultaneously. A modern AMD Zen 5 or Intel Lion Cove core has a pipeline depth of ~20 stages, allowing up to 20 instructions to be in-flight simultaneously. Out-of-order execution goes further by dynamically reordering instructions to avoid pipeline stalls when a later instruction doesn't depend on the result of an earlier one. Branch prediction is critical to pipeline efficiency. When the CPU encounters a conditional branch (if/else, loop), it must guess which path to take before evaluating the condition. Modern CPUs achieve >95% prediction accuracy through sophisticated machine-learning-based predictors. A misprediction flushes the pipeline and wastes ~15–20 cycles — the Spectre vulnerability exploited this exact mechanism. The cache hierarchy reduces memory latency from ~70ns (DDR5 DRAM) to ~4ns (L3 cache) to ~1ns (L2 cache) to ~0.3ns (L1 cache). AMD's 3D V-Cache technology stacks an additional 64MB of L3 cache directly on top of the CPU die using TSV (Through-Silicon Via) interconnects, dramatically improving gaming performance by keeping frequently accessed game data in cache rather than sending it to slower DRAM. Thermal management is critical — modern CPUs at boost frequencies draw 150–300W in a package the size of a postage stamp. The IHS (Integrated Heat Spreader) conducts heat from the die to the cooler. Between die and IHS is thermal interface material (TIM) — Intel solders high-end CPUs (much better conductivity), while some budget chips use thermal paste. Deliding (removing the IHS) and replacing the TIM can reduce temperatures by 20–30°C on some CPUs.